The evolution of Field Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) emulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of an international collaboration, led by Fermilab, that proposed with the contribution of the system described in this work, a Level 1 (L1) trigger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high-speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate (BER) of the MGTs. The system is operational and was already used to emulate the CMS Silicon Tracker data and helped the demonstration of an L1 Trigger approach. This work describes the demonstration performed as case of study, which used the DSS as upstream system and tested the trigger data delivery as a downstream. In the case study, both DSS and the proposed trigger are performed by the same ATCA hardware and the Pulsar 2b. The case study focused to describe the communication between the Data Sourcing shelf and the Pattern Recognition shelf. Data Sourcing reached those requirements for the demonstration and provided a user interface that allows the trigger developers to insert control signals or to perform W/R operations inside Pulsar 2b FPGA block memories.